1. Semiconductor Design Engineer 3

contract basis thirdparty payroll artech

Experience: 6+ Years

Education: BE / M.Tech

Location: Hyderabad

CTC: 25 LPA

JD / Required Skills

* Developing and understanding building block schematics and memory schematics

- Circuit simulation using SPICE simulators, including DC and transient analysis
- Deciphering circuit behavior from schematics
- Circuit characterization, timing libraries, timing files/formats, and timing arcs
- Verilog MOS switch-level models
- Netlist simulation with zero delay, unit delay, and path delay
- Static Timing Analysis
- Gate-level simulations with SDF back annotation
- Debugging SDF annotation issues and ensuring good annotation coverage
- Latch-based designs and timing requirements
- Debugging gate-level simulation failures and root-cause analysis
- What-if analysis and validating fixes at gate or transistor level
- SystemVerilog Assertions
- Gate-level simulation and SPICE correlation
- Debug failures and provide fixes at gate or transistor level, as applicable
- UVM is a plus
- Solid verbal and written communication skills
- Ability to collaborate across sites and global teams

Pay: Up to ₹2,500,000.00 per year

Work Location: In person

📌 Semiconductor Design Engineer 3 (Hyderabad)
🏢 Clock Edge Technologies Pvt Lt
📍 Hyderabad