Job Title: RTL Integration Engineer – PCIe Gen5 to Gen8

Experience: 8–12+ Years

Job Type: Full-Time

Industry: Semiconductor / SoC / VLSI

Job Location: [Location]

Job Summary

We are looking for a highly experienced RTL Integration Engineer with strong expertise in PCIe Gen5 and above to work on advanced SoC and chiplet-based designs.

The ideal candidate should have hands-on experience integrating PCIe controllers and PHYs, strong understanding of PCIe protocol architecture, RTL/SoC integration, and experience supporting designs through silicon bring-up and debug.

Key Responsibilities

- Integrate PCIe Gen5+ controllers and PHYs into complex SoC architectures.
- Own RTL integration including parameterization, clocking, reset and CSR integration.
- Work with PCIe protocol layers including TL, DL, PHY and LTSSM.
- Handle PCIe speed/width changes, recovery and reset scenarios.
- Integrate and debug PIPE 4.x / 5.x PHY interfaces.
- Support error handling, replay mechanisms and AER reporting.
- Optimize PCIe performance, latency and power across multiple VCs and traffic classes.
- Work closely with DV, PHY, firmware and software teams.
- Support silicon bring-up, debug and visibility/instrumentation activities.
- Contribute to PCIe compliance and system-level integration.

Mandatory Skills
- Strong hands-on experience in PCIe Gen5+ RTL integration.
- Strong understanding of PCIe architecture – Root Complex, Endpoint and Switch.
- Good knowledge of LTSSM states, transitions and recovery mechanisms.




- Robust understanding of TLP, DLLP, flow control, replay and ordering.
- Experience with PIPE interface and PCIe PHY integration.
- Experience with CDC, multi-clock design and reset sequencing.
- Knowledge of ASPM – L0s, L1, L1.1 and L1.2.
- Understanding of AER, RAS and PCIe error handling.
- Experience integrating PCIe with AXI/APB-based SoC fabrics.
- Silicon-proven PCIe Gen5+ experience is mandatory.

Gen-Specific Experience

PCIe Gen5

- 32 GT/s NRZ operation
- Equalization awareness
- High-speed timing considerations

PCIe Gen6

- FLIT-mode architecture
- PAM4
- FEC/CRC
- PHY latency considerations

PCIe Gen7/Gen8

- Scalable RTL architecture
- Retimer/chiplet awareness
- Reliability and RAS considerations

Preferred Skills
- PCIe Gen6 FLIT-mode experience
- CXL 2.x / 3.x awareness
- Retimer/Redriver integration
- Chiplet / multi-die SoC experience
- Post-silicon debug and silicon bring-up
- Security concepts such as IDE and link-level protection

Education Bachelor's / Master's degree in Electrical Engineering, Electronics, VLSI, Computer Engineering or a related field.

Important

Candidates should have hands-on PCIe Gen5+ RTL integration experience. Profiles with only PCIe verification, PCIe Gen3/Gen4 experience, or generic RTL design experience may not be considered.

Apply Now with your updated resume highlighting your PCIe generation, RTL integration, PHY/PIPE and silicon experience.

Pay: From ₹50,000.00 per month

Work Location: In person

📌 RTL Integration Engineer – PCIe Gen5 to Gen8 (Bengaluru)
🏢 ORGLINKED India Pvt.Ltd
📍 Bengaluru