Company Description Cadence is a market leader in AI and digital twins, applying advanced computational software to accelerate innovation in silicon and system design. Guided by its Intelligent System Design™ strategy, Cadence provides critical design solutions that enable leading semiconductor and systems companies to create next-generation products across markets such as hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences, and robotics.

Its technologies span from chip-level design to full electromechanical systems, supporting complex, high-performance engineering workflows. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies, highlighting its strong leadership and operational excellence. The company offers broad opportunities for technical growth and collaboration; more information is available at www.cadence.com.

Role Description This full-time, on-site RTL Design Verification Engineer role is based in Delhi, India. The role involves developing and executing verification plans for complex RTL designs, including testbench creation, simulation, and coverage analysis to ensure functional correctness and design quality.

Daily responsibilities include performing functional and formal verification, debugging failures, analyzing root causes, and collaborating closely with RTL designers and architecture teams to refine specifications and resolve issues. The engineer will contribute to verification methodology improvements,



maintain documentation for verification flows, and support sign-off criteria for tape-out readiness. Participation in design and verification reviews, continuous refinement of verification environments, and alignment with project schedules are integral to this position.

Qualifications

- Candidates should possess robust RTL Design skills and a solid understanding of digital logic and hardware description languages (e.g., Verilog, SystemVerilog).
- Candidates should possess expertise in Functional Verification, including testbench development, constrained-random testing, and coverage-driven methodologies.
- Candidates should possess competency in Formal Verification techniques and tools to complement simulation-based verification.
- Candidates should possess knowledge of Computer Architecture concepts such as pipelines, caches, memory hierarchies, and bus protocols.
- Candidates should possess advanced Debugging skills for simulation failures, waveform analysis, and root-cause identification.
- Relevant qualifications include a bachelor’s or master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
- Beneficial skills include familiarity with scripting languages (e.g., Python, Perl, Tcl), EDA tools and flows, and version control systems.
- Strong analytical thinking, attention to detail, collaborative communication, and the ability to work effectively in a cross-functional engineering team are essential.

📌 RTL Design Verification Engineer (Delhi)
🏢 Cadence
📍 Delhi