- Work with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
- Co-work with Place & Route team to resolve full-chip layout integration issues.
- Work with various implementation team to drive Physical Verification
- Coordinates with internal IP owners on IP related issues.
- Coordinates with Manufacturing Team on DRC related issues.
- Provide automation solutions to improve efficiency in tape-out flow.
- Report on tapeout issues.
- Custom Layout
Requirement
- Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science
- 3-6 years of physical verification or design experience
- Preferably well-versed in Calibre, ICV
- Proficient in script programming, such as, Tcl, Perl or C-shell
- Proficient in UNIX (Linux) platforms
- Track record of successful tapeout of chips
- Solid communication skills, problem solving and analytical skills