- Role Level: Lead Full-Time
- Location: Vijayawada / Hybrid (Flexible)
- Experience: 4+ years in Full-Custom AMS Physical Layout & Multi-Foundry Physical Verification

Role Overview

Own end-to-end physical implementation: full-custom analog layout, automated digital place-and-route,

full-chip (analog + digital) integration, foundry PDK bring-up, power grid synthesis (PDN),

electromigration/IR-drop analysis, and DRC/LVS sign-off on advanced nodes — bringing 100% of the tape-out physical design flow in-house without reliance on an external design partner.

Key Responsibilities

- Foundry PDK Setup & Customization: Install and verify foundry PDKs, techfiles, cds.lib, display.drf,

layer maps, and symbol libraries for custom physical design.
- Floorplanning and full-custom physical layout of fine-pitch sensor pixel arrays, high-speed column

SAR ADC banks, bandgap references, and I/O pad rings on advanced nodes.
- Multi-Vendor Physical Verification Sign-Off: Execute golden DRC, LVS, ERC, Antenna, and DFM physical verification using Siemens Calibre Interactive / RVE and Synopsys IC Validator (ICV),

ensuring zero DRC/LVS violations prior to tape-out.
- Perform parasitic extraction (PEX / xACT / xRC) and generate clean Calibre/ICV runset reports and extracted netlists for post-layout SPICE re-simulation.
- Execute Power Distribution Network (PDN) routing, agile IR-drop analysis, electromigration

(EM) checks,



and substrate noise isolation.
- Implement active metal shielding, ESD protection clamps, and anti-tamper physical layout structures to ensure robust physical integrity.
- Own foundry PDK bring-up and technology file installation, corner library validation, and DRC/LVS rule deck qualification for each new process node or PDK revision — the hands-on execution layer beneath the Chief Silicon Architect's PDK customization oversight.
- Administer the team's core EDA license server (FlexLM/FlexNet) and keep Cadence, Siemens

Calibre, and Synopsys tool installs current — a lightweight collateral duty at this team size (single license manager and shared design server, not a dedicated compute grid).

Qualifications & Technical Skills:

- B.Tech / M.Tech in Electronics / VLSI Design or equivalent industry experience.
- 4+ years of hands-on expertise in full-custom Analog/Mixed-Signal physical layout and tape-out sign-off.
- Experience in layout automation using SKILL / Python / TCL scripting and Parameterized Cells

(PCells) for array generation.
- Deep mastery of Siemens Calibre (Calibre DRC, Calibre LVS, Calibre PEX, Calibre DFM) and Calibre

RVE debugging workflows.
- Working familiarity with Synopsys IC Validator (ICV) and Cadence Pegasus / Quantus toolchains.
- Mastery of Cadence Virtuoso Layout XL / GXL and parasitic extraction flows.

📌 Physical Layout & DRC/LVS Sign-Off Lead (Vijayawada)
🏢 Qailash Labs
📍 Vijayawada