Role Description This is a full-time, in office Physical Design Engineer with DDR role with 6+ year experience based in Bengaluru South. The role involves implementing and optimizing physical design for complex SoC blocks, with a focus on DDR subsystems, including floorplanning, placement, clock tree synthesis, routing, and timing closure. The engineer will collaborate with logic, circuit, and verification teams to review RTL, define constraints, and resolve design and timing issues.

Daily work includes running physical verification checks, addressing DRC/LVS/EM/IR violations, and ensuring design sign-off quality. The role also requires creating and maintaining documentation, participating in design reviews, and contributing to continuous improvement of physical design flows and methodologies.

Relevant Skills

- Strong Physical Design skills, including floorplanning, placement, CTS, routing, and timing closure for high-speed interfaces such as DDR.
- Experience with Physical Verification, including DRC, LVS, EM/IR analysis,



and sign-off using industry-standard EDA tools.
- Solid understanding of Logic Design and Circuit Design principles for digital integrated circuits and memory interfaces.
- Proficiency in RTL Design concepts, constraints development (SDC), and interaction with front-end design teams.
- Hands-on experience with industry tools (e.g., Synopsys, Cadence, or similar) for backend implementation and verification.
- Knowledge of SoC design flows, power optimization techniques, and clocking strategies for large-scale designs.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field, or equivalent practical experience.
- Ability to work collaboratively in cross-functional teams, communicate clearly, and take ownership of design deliverables.

Pay: ₹1,100,000.00 - ₹1,500,000.00 per year

Benefits

- Provident Fund

Work Location: In person

📌 Physical Design Engineer (Bengaluru)
🏢 G7N semiconductor
📍 Bengaluru