Lead Physical Design Engineer Physical implementation for ASIC, SoC and IP core programmes floorplan through signoff.
Job Details
Job type: Full time. Experience: 8+ years. Location: Bengaluru, India.
The Work
What the role involves
- Floorplanning, placement, clock tree synthesis, routing and timing closure across multiple corners.
- Power integrity, IR analysis and physical verification through to DRC and LVS signoff.
- Working within foundry PDKs across mature and advanced nodes.
A CV is fine. What helps more is a paragraph about a problem you solved that was harder than it looked, and what you would do differently now.
Common Questions
Where is this role based
Bengaluru, India. Full time.
What experience is expected
8+ years. The range is a guide rather than a filter; make the case if you are outside it.
How do I apply
Write to with the role title in the subject,
and include a paragraph about a problem you solved that was harder than it looked.
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Related work
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