Job Title: Physical Design (PD) Engineer

Location: Bangalore

Experience: 6+ Years

Employment Type: Full-Time

Work Mode: Work from Office

CTC: ₹24–30 LPA

Job Overview

Juntran Technologies is looking for an experienced Physical Design (PD) Engineer with strong hands-on expertise in ASIC/VLSI Physical Design and end-to-end physical implementation. The ideal candidate should have experience handling the complete Netlist-to-GDSII flow and be proficient in timing, power, congestion, and physical signoff activities.

Key Responsibilities

Execute complete Netlist-to-GDSII Physical Design implementation flow.

Perform floorplanning, macro placement, design partitioning, and power planning.

Optimize standard-cell placement and address congestion issues.

Perform Clock Tree Synthesis (CTS) and clock optimization.

Handle global and detailed routing.

Drive setup and hold timing closure across multiple corners and modes.

Perform MCMM analysis and timing ECOs.

Work on STA, SDC constraints, and timing optimization.

Perform physical verification including DRC/LVS.

Analyze and optimize IR Drop and Electromigration (EM) issues.

Support physical design signoff and ensure design quality and performance.

Collaborate with RTL, STA, DFT, and other cross-functional teams as required.





Required Skills

6+ years of relevant experience in Physical Design / Physical Implementation.

Strong hands-on experience in ASIC/VLSI Physical Design.

Robust understanding of the complete Physical Design flow from Netlist to GDSII.

Experience with:

Floorplanning & Macro Placement

Power Planning

Placement Optimization

CTS & Clock Optimization

Routing

Timing Closure

MCMM

Timing ECOs

Congestion Optimization

STA & SDC

DRC/LVS

IR Drop & EM

Physical Verification & Signoff

Hands-on experience with tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime/Tempus, or equivalent tools.

Preferred Qualifications

Experience with Intel.

Experience working on complex ASIC/SoC designs.

Exposure to advanced technology nodes.

Experience handling large-scale chip/block implementation.

Strong expertise in timing, congestion, and power optimization.

Why Join?

Opportunity to work on complex ASIC/SoC projects.

Exposure to advanced Physical Design and implementation flows.

Opportunity to work with industry-standard EDA tools.

Professional growth and challenging technical assignments.

Apply Now

? Email: [email protected]

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