Hiring: Digital Design Verification Engineer

Location: Noida, India

Experience: 8–12+ Years

Open Positions: 3

Job Summary

We are looking for experienced Digital Design Verification Engineers to join our client's semiconductor engineering team in Noida.

The role involves functional and performance verification of complex IP, Subsystem, SoC and System-level designs using advanced verification methodologies. The ideal candidate should have strong hands-on experience in SystemVerilog, UVM, RTL verification, coverage-driven verification and debugging.

A strong zero-defect mindset, analytical approach and ability to translate specifications into a traceable verification plan are essential.

Key Responsibilities

- Develop verification plans based on design specifications and requirements.
- Develop and implement SystemVerilog/UVM-based verification environments.
- Develop verification components including drivers, monitors, scoreboards and checkers.
- Develop directed and constrained-random test cases.
- Work with UVM VIPs and verification components.
- Develop and analyze functional and code coverage.
- Develop and implement SystemVerilog Assertions (SVA).
- Perform regression management, failure analysis and debugging.
- Analyze RTL and gate-level designs to identify functional issues.
- Perform formal verification where applicable.
- Support verification at IP, subsystem and SoC levels.
- Work closely with global SoC/IP design and verification teams.
- Perform root-cause analysis and reproduce failures.
- Contribute to verification sign-off and continuous improvement of verification methodologies.





Required Skills
- 8–12+ years of experience in SoC/IP/Subsystem verification.
- Strong hands-on experience in SystemVerilog and UVM.
- Good knowledge of Verilog/VHDL and industry-standard simulators.
- Solid understanding of RTL design and debugging.
- Experience in functional and performance verification.
- Strong knowledge of coverage-driven verification and regression management.
- Experience with SystemVerilog Assertions (SVA).
- Understanding of formal verification methodologies.
- Experience with complex designs involving multiple clocks and power domains.
- Strong debugging, logical analysis and root-cause analysis skills.

Preferred / Good-to-Have Skills Experience in one or more of the following will be an added advantage:
- ARM / Microcontroller architecture
- AMBA / AHB / AXI / ACE
- Cache coherency
- PCIe
- DDR3/DDR4/LPDDR
- Flash / SRAM / Memory Controllers
- MIPI
- Ethernet
- USB
- GPU / VPU
- UPF / CPF and low-power verification
- Palladium / Zebu / FPGA prototyping
- AVIP
- PinMux verification
- Randomization

Education B.Tech / B.E / M.Tech in Electronics, Electrical, Computer Science, VLSI or a related engineering discipline.

Candidate Profile

We are looking for candidates with strong hands-on expertise in Digital Design Verification, particularly those who have worked on complex IP, subsystem or SoC-level verification environments.

Candidates with experience in SystemVerilog + UVM + RTL debugging + functional coverage + protocol verification are encouraged to apply.

Pay: From ₹45,000.00 per month

Work Location: In person

📌 Digital Design Verification Engineer (Noida)
🏢 ORGLINKED India Pvt.Ltd
📍 Noida