We are looking for a skilled Design Verification Engineer with 5+ years of experience in ASIC/SoC verification. The ideal candidate will have strong expertise in SystemVerilog, UVM, and functional verification methodologies, with a passion for delivering high-quality silicon solutions.
Key Responsibilities
- Develop and execute verification plans for ASIC/SoC designs.
- Build and maintain UVM/SystemVerilog-based testbenches.
- Perform RTL verification using VCS, Xcelium, Questa, or ModelSim.
- Debug simulation failures and drive coverage closure.
- Collaborate with design teams to resolve functional issues.
- Contribute to verification reviews and best practices.
Required Skills
- 5-10 years of ASIC/SoC Design Verification experience.
- Solid hands-on experience in SystemVerilog and UVM.
- Good understanding of digital design fundamentals.
- Experience with simulation, debugging, and coverage analysis.
- Knowledge of scripting languages such as Python, Perl, or TCL is a plus.
- Strong analytical and communication skills.
Preferred
- Experience with protocols such as PCIe, DDR/LPDDR, Ethernet, USB, AXI, MIPI, or SATA.