Position: Design Verification Engineer (BB810FF RM 4431)

About The Role

We are looking for an experienced Design Verification Engineer to join a high-speed networking ASIC programme on a contract basis. You will work as part of a team verifying complex IP blocks and subsystems, contributing independently from day one. The role requires strong hands-on UVM and System Verilog skills, with networking domain exposure considered a significant advantage.

Key Responsibilities

- Verification environment development: Design, develop, and maintain UVM-based testbenches for IP and subsystem verification from scratch.

- Test plan ownership: Write and maintain verification plans, coverage plans, and test specifications from architecture and micro-architecture documents.

- Constrained-random testing: Develop directed, constrained-random, stress, error-injection, and cornercase test cases.

- Coverage closure: Drive functional coverage and code coverage closure; implement SVA assertions for protocol and design intent checking.

- Regression management: Set up and maintain regression infrastructure; debug and root-cause regression failures promptly.

- Bug reporting: Identify, document, and track design bugs; collaborate with RTL designers to verify fixes.

- Cross-functional collaboration: Work closely with RTL design and firmware teams to clarify design intent and resolve verification gaps.

Requirements

Must Have

- System Verilog & UVM: Very good knowledge of SystemVerilog and UVM methodology — environments, agents, sequences,



drivers, monitors, scoreboards, and functional coverage.

- Experience band: 8–10 years of ASIC design verification experience at IP, subsystem, and SoC level.

- Simulators: Hands-on experience with Synopsys VCS and Verdi for simulation and waveform debug.

- Verification flow: Familiarity with constrained-random verification, coverage-driven verification, assertionbased verification, and regression closure.

- India-based: Available to work from office Tuesday, Wednesday, and Thursday each week.

- Communication: Strong English communication skills; ability to collaborate with distributed teams and work independently.

Valuable to Have

- Networking domain exposure: Experience or exposure to networking-related verification — Ethernet, MACsec, IPSec, PCIe, high-speed serial interfaces, or switching ASIC verification.

- Scripting: Python, Perl, or Shell scripting for test automation, regression infrastructure, or coverage analysis.

- GLS / formal: Gate-level simulation experience; exposure to formal verification tools (JasperGold or equivalent).

- RAL: Experience using UVM Register Abstraction Layer (RAL) for register-level verification.

- SoC-level verification: Experience at SoC integration level — connectivity verification, chip-level test cases, or emulation-based validation (HAPS, Palladium, Veloce).

- Hardware–firmware co-verification: Experience verifying firmware-driven hardware using C-DPI or mixedlanguage testbenches.

📌 Design Verification EngineerFF RM 4431) (Bengaluru)
🏢 Source right
📍 Bengaluru