Design Verification Engineer - SystemVerilog/UVM (India)

Design Verification Engineer - SystemVerilog/UVM (India)

24 Sep
|
RANGAM INFOTECH
|
India

24 Sep

RANGAM INFOTECH

India

Role Overview :

We are looking for an experienced Design Verification Engineer with strong hands-on expertise in SystemVerilog, UVM, simulation-based verification, and advanced verification methodologies. The role will involve developing and executing verification strategies for complex IP/SoC designs, debugging simulation failures, driving verification closure, and collaborating closely with Design, Architecture, Firmware, Validation, and Physical Design teams.

Key Responsibilities :

- Develop and maintain scalable SystemVerilog/UVM-based verification environments for IP and SoC designs.
- Define verification strategies, test plans, test scenarios, and coverage goals based on design and architecture specifications.
- Develop reusable testbenches, sequences, monitors, drivers, scoreboards, assertions, and coverage models.
- Execute functional and regression simulations and analyze failures to identify root causes.
- Debug complex RTL and simulation issues using industry-standard simulation and waveform-debugging tools.
- Drive verification activities through coverage closure,



defect resolution, and sign-off.
- Support verification of high-speed interfaces such as PCIe and UCIe, and connectivity protocols such as USB 2.0/3.0/3.1 and SD/uSD.
- Develop automation and utility scripts using Python, Shell, Tcl, or equivalent scripting languages.
- Support basic integration and debugging of hardware emulation platforms such as Palladium and Zebu.

Required Skills :

- 8 - 12 years of experience in ASIC, SoC, IP, or semiconductor design verification.
- Strong hands-on expertise in SystemVerilog and UVM.
- Experience with constrained-random verification, assertions, coverage, and regression management.
- Proficiency in Python; Tcl/Perl experience is an advantage.
- Working knowledge of Linux/Unix environments and shell scripting.
- Experience with hardware emulation platforms like Palladium or Zebu.
- Robust analytical, troubleshooting, and communication skills.

📌 Design Verification Engineer - SystemVerilog/UVM (India)
🏢 RANGAM INFOTECH
📍 India

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