Design Verification Engineer-1 (Hyderabad)

Design Verification Engineer-1 (Hyderabad)

24 Sep
|
Clock Edge Technologies Pvt Lt
|
Hyderabad

24 Sep

Clock Edge Technologies Pvt Lt

Hyderabad

Design Verification Engineer-1

Location: Hyderabad

Positions: 3

contract job , thirdparty payroll

Experience & Budget

* 0–2 Years: 15 LPA

- 3–5 Years: 18 LPA
- 5+ Years: 22 LPA

Required Skills & Experience

* Digital/Analog Circuits
- SystemVerilog (SV) / UVM
- Verilog
- CMOS Concepts
- Pre-Silicon Verification
- Gate-Level Simulation (GLS)
- Assertions
- Debug
- Regression
- EDA Tools & Cross-Team Collaboration
- Robust hands-on experience in SV/UVM
- Hands-on ownership of SoC/Full-Chip Pre-Silicon DRAM Verification
- Proven Debug Depth and Regression Optimization
- Comfortable with EDA Tools and Cross-Team Execution

Pay: ₹1,500,000.00 - ₹2,200,000.00 per year

Work Location: In person

📌 Design Verification Engineer-1 (Hyderabad)
🏢 Clock Edge Technologies Pvt Lt
📍 Hyderabad

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