Role Description 1–4 years of experience in ASIC/SoC Functional Verification. Strong proficiency in SystemVerilog and UVM. Good understanding of digital design fundamentals and verification methodologies.
Experience with Verilog/SystemVerilog simulation and debugging. Knowledge of constrained-random verification and functional coverage. Familiarity with scripting languages such as Python, Perl, or Shell is an added advantage. Positive debugging, analytical, and problem-solving skills. Excellent communication and teamwork skills.
Preferred Qualifications Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field. Exposure to industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens QuestaSim. Knowledge of standard bus protocols such as AXI, AHB, APB, PCIe, USB, I2C, SPI, or UART is preferred.