Key Responsibilities

1. Mixed-Signal Co-Simulation: Run full-chip or block-level simulations combining analog solvers and digital engines using tools such as Cadence AMS Designer/Xcelium or Synopsys VCS.
2. Behavioral Modeling: Develop high-level analog behavioral models using Verilog-AMS, Verilog, or SystemVerilog Real Number Modeling (RNM/wreal).
3. Testbench Development: Build metric-driven verification environments using System Verilog and UVM-AMS methodologies.
4. Debugging and Coverage: Analyze analog and digital interface issues, waveform anomalies, simulation convergence failures, and drive functional coverage closure.
5. Automation: Develop scripts in Python, Perl, or Tcl to automate verification flows, regression management, and reporting.
6. Model vs. Schematic Verification: Develop and execute verification plans to ensure functional equivalence between high-level behavioral models and transistor-level schematics.
7. Mixed-Mode Configuration Management:



Configure and execute mixed-mode simulations where selected blocks run at schematic/SPICE level while the remaining design runs using behavioral models.

Required Skills and Qualifications:
1. Programming and Verification Languages:
2. SystemVerilog, UVM, Verilog/Verilog-AMS/SystemVerilog RNM (Real Number Modeling)
3. Domain Knowledge:
4. DLL (Delay Locked Loop), DCC (Duty Cycle Corrector), ZQ Calibration, Bandgap, ADCs (Analog-to-Digital Converters), DACs (Digital-to-Analog Converters), PLLs (Phase Locked Loops), LDOs (Low Dropout Regulators)
5. EDA Tools:
6. Cadence Virtuoso, Spectre, Xcelium.
7. Education and Experience:
8. Robust background and hands-on experience in mixed-signal/Co-sim verification.

Employment Type - Contract period of 1 year. Job Location - Bangalore / Hyderabad.

Notice period - Immediate joiner to 45 days Max.

📌 ASIC Engineer (Design & Verification) role (Bengaluru)
🏢 Anlage Infotech
📍 Bengaluru