Preferred candidate profile

Minimum Qualifications

- Bachelors or master’s degree in electrical engineering, Electronics Engineering, or a related field. Master’s degree strongly preferred

- 12-16 years of industry experience with hands-on experience in digital design including FSM and CPU sub-systems, complex SOCs and FPGA validation

- Strong technical leadership Experience of minimum 6 years

- Familiarity with protocols such as SPI, I2C, APB, AXI, or similar interfaces and high-speed SerDes, Ethernet, D2D PHY IP, and protocols.

- Strong knowledge of ASIC/SoC design flow, including RTL development using SystemVerilog, simulation, lint, CDC/RDC, synthesis, formal/equivalence checking, DFT, and implementation handoff

- Good understanding of full front-end design and development as well as exposure to full suite of backend tools such as CDC, synthesis, LEC, DFT etc.

- Strong teamwork, communication, and organizational skills. Solid analytical, problem-solving, and debugging skills.

📌 ASIC Digital Design Leader :: CISCO (Pune)
🏢 Naukri e-Hire
📍 Pune