Company Description AndGate Informatics Pvt. Ltd. is led by industry professionals with extensive experience in semiconductor, embedded systems, IT/software, and recruitment and staffing.

The company delivers technological solutions and talent services across multiple domains, including ASIC design and verification, physical design, analog and mixed-signal engineering, FPGA, embedded and IoT, database engineering, and AI/ML. With more than 20 years of experience in India and overseas, AndGate Informatics supports clients in India, Malaysia, Singapore, Vietnam, Taiwan, the US, and the UK. A global team collaborates across these verticals, offering specialized expertise to leading technology organizations.

Role Description The Analog Layout and Memory Characterization Engineer will design, implement, and optimize analog and mixed-signal layout blocks and memory circuits for semiconductor products. Day-to-day responsibilities include creating and reviewing analog and memory layouts, performing design rule checks (DRC), layout versus schematic (LVS) checks, and parasitic extraction, and collaborating closely with circuit designers to ensure performance, yield, and reliability targets are met.

The engineer will conduct characterization and validation of memory IP, analyze silicon data, and support debug and optimization activities. This is a full time on-site role based in Noida,



requiring close coordination with cross-functional teams and participation in design reviews and project milestones.

Qualifications

- Candidates should possess strong skills in analog and mixed-signal circuit layout, including experience with memory (SRAM, ROM, eNVM) structures and layout optimization.
- Candidates should possess proficiency with industry-standard EDA tools for layout and verification (e.g., Cadence, Synopsys, Mentor), including DRC, LVS, and parasitic extraction flows.
- Candidates should possess capabilities in memory characterization, silicon validation, data analysis, and debugging of performance, power, and reliability issues.
- Candidates should possess knowledge of CMOS process technologies, device physics, design for manufacturability, and reliability considerations for advanced nodes.
- Candidates should possess strong problem-solving, documentation, and communication skills, with the ability to collaborate effectively in cross-functional engineering teams.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related field is preferred; prior experience in analog layout or memory IP design/characterization is an advantage.
- Familiarity with scripting (e.g., Python, Perl, or TCL) to automate layout or characterization tasks and experience working in global, multi-site environments will be beneficial.

📌 Analog Layout And Memory Characterization Engineer (Noida)
🏢 AndGate Informatics
📍 Noida