Hiring Location: Bangalore

Experience: 8-12 Years

We are seeking a Staff DFT Engineer who can own and drive the complete DFT strategy for complex SoCs from architecture through production silicon. This role requires deep hands-on expertise, strong technical judgment, and the ability to lead and mentor junior engineers while collaborating cross-functionally with design, PD, validation, and manufacturing teams.

The ideal candidate operates independently, makes architecture-level decisions, and is accountable for test quality, coverage, and silicon readiness.

Responsibilities:

DFT Architecture & Planning

- Own DFT architecture definition at chip and subsystem level
- Define scan, compression, LBIST, MBIST, boundary scan, and test access strategies
- Drive testability requirements early in the RTL design phase
- Balance coverage, test time, power, area, and schedule tradeoffs

- DFT Implementation (End-to-End Ownership)

- Lead and execute:
- Scan insertion, stitching, and DRC closure
- ATPG (stuck-at, transition, path delay)
- Test compression and pattern optimization
- Own DFT signoff including coverage, IR drop, power, and timing impacts
- Debug and resolve DFT issues across RTL, synthesis, P&R;, and gate-level stages

- ATPG & Test Quality

- Generate, analyze, and optimize ATPG patterns
- Achieve high fault coverage with minimal pattern count
- Review and sign off on:
- Fault coverage reports
- Pattern volume and test time
- Diagnose coverage holes and drive design or methodology fixes

- Silicon Bring-Up & Production Support

- Support first silicon bring-up, failure analysis, and yield ramp
- Debug scan, BIST, and tester-related failures




- Collaborate with ATE and manufacturing teams to improve yield and test robustness
- Drive ECOs for DFT-related silicon issues

- Technical Leadership & Mentorship

- Act as DFT technical lead for one or more chips
- Guide and review work of junior and senior DFT engineers
- Define best practices, checklists, and reusable DFT methodologies
- Provide technical direction and design reviews

- Cross-Functional Collaboration

- Work closely with:
- RTL designers
- Physical design (PD)
- Functional verification
- Product engineering and manufacturing
- Communicate DFT requirements and risks clearly to stakeholders

- Preferred/Nice-to-Have Experience:

- Experience with high-volume production test, ATE bring-up, and test cost optimization.
- Exposure to safety-critical applications (automotive, industrial) and standards (e.g., ISO 26262) from a test/reliability standpoint.
- Experience with on-chip debug, trace, and design-for-debug features.
- Scripting skills in Python/Tcl/Perl for DFT automation, log analysis, and flow integration.
- Prior experience mentoring or leading small DFT teams or task forces.

- Qualifications and Experience:

- Proven experience in leading DFT teams through end-to-end SoC execution, from architecture to silicon bring-up.
- Demonstrated expertise in developing DFT architecture from scratch for complex SoC designs.
- Robust team management and leadership experience with a track record of mentoring and growing engineering talent.
- Bachelor's or Master’s degree in Electrical/Electronics Engineering or a closely related field.
- 7+ years of hands-on experience in DFT methodologies and industry-standard test techniques.
- Deep knowledge and hands-on experience with:

📌 DFT Engineer (Bengaluru)
🏢 Capgemini Engineering
📍 Bengaluru