Job Description
SRAM Memory Layout Engineer
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nExperience: 3–6 Years
nLocation: Bangalore
nNotice Period: Immediate to 60 Days
nTechnology: TSMC 2nm/3nm | Samsung 2nm/4nm
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nJob Description
nWe are looking for experienced SRAM Memory Layout Engineers with strong hands-on expertise in advanced-node memory layout and physical verification. The ideal candidate should have experience working on SRAM macros and memory structures from layout development through tape-out.
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nKey Responsibilities & Skills
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3–6 years of hands-on experience in SRAM Memory Layout .n
Strong experience with Single Port, Dual Port, Pseudo Dual Port SRAM, Register File, FIFO, and Embedded Memory macros .n
Hands-on experience with TSMC 2nm/3nm and/or Samsung 2nm/4nm technology nodes.n
Develop and integrate bit-cell arrays, sense amplifiers, decoders, column muxes, row/column periphery, and top-level memory blocks .n
Experience across the complete layout lifecycle, including floorplanning, placement, routing, optimization, DRC/LVS/ERC, PEX,



and tape-out .n
Strong knowledge of matching, symmetry, EM/IR, density, antenna, ESD, and advanced-node design rules .n
Proficiency in Cadence Virtuoso and Calibre DRC/LVS/PEX .n
Experience in area, performance, power, yield, and reliability optimization .n
Robust debugging skills with hands-on experience in PV issue resolution and ECO implementation .n
Good scripting skills in Tcl/Python for layout automation and flow improvement will be an added advantage.n
Ability to collaborate effectively with Memory Design, Circuit Design, and Verification teams .n

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nPreferred Candidate Profile
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Solid understanding of advanced-node SRAM layout methodologies .n
Good problem-solving and debugging skills.n
Ability to independently handle layout tasks and resolve physical verification issues.n
Solid communication and cross-functional collaboration skills.n

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📌 Sram Memory Layout Engineer Bengaluru
🏢 Modernize Chip Solutions (MCS)
📍 Bengaluru