- Hands-on experience and very positive understanding of DDRPHY architecture, DFI protocol and Jedec standards for latest Gens.
- Experience in verification and general computational logic design/verification concepts.
- Working Experience on LPDDR5/LPDDR4 (Must)
- Expertise in Verilog/System Verilog and UVM/OVM.
- Strong debugging, Analytical and problem-solving skills.
- Experience in Scripting languages like Perl would be a plus.
- Post-si bring-up and HW-SW debug experience would be a plus.
Responsibilities:
- Testplan to Vector Delivery all the assigned task ownership and closure.
- Debug of regression signatures and identifying bug fixes.
- Responsible for Quality sign-off and required documentation.
- Debug and root cause SS/SOC/post silicon issues in collaboration with Design teams.
- Understanding of standard bus protocols like AHB, AXI protocols would be a plus.
- Having the right attitude to learn and quickly adapt to changing industry trends