Job Location: BangaloreThis role is for a Memory Layout Engineer with 3-7 years of experience to design and develop memory blocks for integrated circuits (ICs). You will be responsible for creating effective memory layouts that meet performance, power, and area constraints.
Responsibilities:
Design memory layouts for various building blocks including:Bit cell arrayRow decoderColumn decoderSense amplifiersInput/Output (I/O) blocksIntegrate top-level memory blocksPerform physical verification using tools like Design Rule Check (DRC) and Layout Versus Schematic (LVS)Ensure layouts meet Design for Manufacturability (DFM) and Design for Yield (DFY) requirementsAnalyze layouts for potential power and signal integrity issuesMay involve scripting using languages like PERL, Shell, TCL, or Skill
Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering,
or a related field3-5 years of experience in memory layout designProven experience with memory layout tools like Cadence Virtuoso and AssuraUnderstanding of memory compiler architectures and sub-blocksExperience with low-power, high-performance, and high-density SRAM memory design (experience with different technology nodes is a plus)Knowledge of Design for Manufacturability (DFM) and Design for Yield (DFY) conceptsStrong analytical and problem-solving skillsExcellent communication and teamwork abilities
Preferred Skills:
Experience with custom and compiler-based memory layoutExperience with FinFET process technologiesExperience with memory verification methodologies
Requirements added by the job poster• 3+ years of work experience with SRAM• 3+ years of work experience with Layout Design