STA Lead

Location: Bangalore

Job Description:

- Lead and execute Static Timing Analysis (STA) for complex SoC designs.
- Perform timing analysis, timing closure, and sign-off activities.
- Analyze and resolve setup, hold, recovery, removal, and clock-related timing violations.
- Develop and debug SDC constraints and timing constraints.
- Work on MCMM (Multi-Corner Multi-Mode) timing analysis and optimization.
- Perform clock timing analysis, including clock skew, latency, and uncertainty.
- Debug timing issues related to logic, placement, routing, congestion, and CTS.
- Collaborate with Physical Design, Synthesis, DFT, and RTL teams for timing closure.
- Review timing reports and identify critical paths and optimization opportunities.
- Handle ECOs for timing closure and sign-off.
- Work with industry-standard STA tools such as Synopsys PrimeTime and/or Cadence Tempus.
- Participate in methodology development, automation, and flow improvements.
- Mentor junior STA engineers and provide technical leadership.

Experience (years) : 8+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

📌 STA Lead (India)
🏢 Mirafra Software Technologies
📍 India