We are looking for a skilled Physical Design Synthesis Engineer with hands-on experience in RTL synthesis, CLP, and LEC to join our engineering team.
Key Responsibilities:
- Perform RTL synthesis and optimize designs for PPA (Power, Performance, and Area).
- Handle synthesis constraints, timing analysis, and netlist generation.
- Perform CLP (Conformal Low Power) checks and LEC (Logic Equivalence Checking).
- Debug and resolve synthesis, equivalence, and low-power verification issues.
- Collaborate with RTL, DFT, and Physical Design teams to ensure successful design implementation.
Required Skills:
- Experience 3+ years
- Robust knowledge of RTL synthesis and physical design fundamentals.
- Hands-on experience with CLP and LEC.
- Experience with industry-standard EDA tools such as Synopsys or Cadence.
- Good understanding of timing constraints, STA, and low-power design concepts.