About the Role
We are seeking a highly experienced Compiler / Software Architect to join our NPU Hardware Architecture team and play a key role in the hardware-software co-design of next-generation AI inference accelerators.
This is a unique role at the intersection of NPU hardware architecture, AI compilers, performance modeling, and software development. The position will work directly with hardware architects to define, evaluate, and prototype the software stack required to program current and future NPU architectures.
Our NPU architecture is closely coupled with the compiler stack. Efficient utilization of the accelerator requires deep understanding of the hardware compute architecture, memory hierarchy, dataflow, scheduling, quantization, instruction set and execution model. The successful candidate will use this understanding to develop compiler and software proof-of-concepts, evaluate architectural proposals against real AI workloads, and influence the design of future NPU hardware.
You will work closely with hardware architects, micro-architects,
compiler engineers and AI software teams to answer a fundamental question:
How should the NPU hardware and software be co-designed to deliver the best performance, power efficiency, programmability and scalability for real-world AI workloads?
What You Will Be Responsible For
Compiler & Software Architecture for NPU
- Develop compiler and software proof-of-concepts for current and next-generation NPU architectures.
- Define software abstractions and compiler flows that efficiently expose NPU hardware capabilities to AI workloads.
- Develop and evaluate compiler concepts including graph lowering, intermediate representations, operator mapping, scheduling, tiling, fusion, memory planning and code generation.
- Translate NPU architectural concepts into executable software models and demonstrate their feasibility using representative AI workloads.
- Develop lightweight compiler/runtime infrastructure to validate recent h