Remote: Hybrid

Senior SerDes Architect and LeadLocation: Austin / Milpitas / Fort Collins / BillericaHybridWe are at the forefront of Wideband Signal Processing™ delivering high-performance, low-power analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other mixed-signal IP cores. These components are crucial for a wide array of modern applications, including artificial intelligence (AI) infrastructure, advanced wireless communications like:5G networks and optical communicationsAutomotive networking, LiDAR, and radar systemsSatComm, Software Defined Radio (SDR) and other broadband communicationsSeniorSerDes architect and development lead focused on PAM4 ADC and DAC based wireline technologies. The successful candidate in this role will work with customers to understand requirements, and will lead the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications10-20 years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processesThorough familiarity with high-speed PAM4 architectures and topologiesExperience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL, CTLEs,



CDRs, etc.Thorough understanding of equalization techniques (both analog and digital) Must have a track record of successfully taking designs to productionAbility to work with customers to define products that address needsMust have experience with evaluating silicon on bench and familiarity with standard lab equipmentStrong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysisExperience with analog and digital behavioral modeling, and/or synthesis of digital control blocksFamiliar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation toolsMATLAB understanding would be preferred but not mandatoryFamiliar with designing circuits for electromigration and ESD compliance in submicron CMOS processMust be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processesMust be able to work independently, create and adhere to schedulesMust possess robust written and verbal communication skills with an ability to work with teams spread across geographic locationsShould be able to seek help proactively as well as share and pass on knowledgeContact:UdayMulya [email protected]"Mining The Knowledge Community"

📌 Senior Serdes Architect (Karnataka)
🏢 Mulya Technologies
📍 Karnataka