BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
2+ years of Design Verification experience with SV/UVM
Strong background on functional verification fundamentals, setting planning, test plan generation, environment development is a must.
Design Verification experience verifying complex designs and leading projects from concept to verification closure.
Solid hands-on UVM and System Verilog coding experience and functional verification setting development is required.
Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.