Position: PAGLS/PARTL (BB69ST RM 4445)

Job Responsibilities
Responsible for building GLS workplace (Unit delay & Timing) setup
Responsible for bring up Sanity simulations across cores with Unit delay & Timing sims
Work with Architecture, Design team to understand the low power design features and create verification plan
Develop verification components, testbench for low power verification and integrate third party VIPs/UVCs as required
Create constraint random verification workplace using System Verilog, UVM
Perform Power Aware Verification in a random verification environment on the design
Regress and close the required Low Power coverage metrics to ensure high quality design

Minimum Skills
8+ years of Design Verification experience.
Bachelor’s degree in Science, Engineering or closely related field.
3+ years of hands-on experience in System Verilog, OVM/UVM based constrained random verification.
3+ years of hands-on experience in developing GLS environment, GATE ID creation, verification components/UVCs, testbench for GLS verification




3+ years of hands on testbench bring up, integrating third party VIPs, digital design, verification, debugging, and waveform debug
2+ years of experience in UPF based Power Aware verification
2+ years of experience in Functional coverage model development and/or code coverage closure
Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.
Solid communication skills to interact with a global team.

Desirable
BE/ME degree in Electrical Engineering or equivalent.
Experience with Synopsys NLP (native Low Power) tool.
Working knowledge of GLS, PAGLS and scripting languages such as Perl, Python is a plus.
Worked on Low Power coverage metrics collection and coverage closure
Post-Silicon debug experience.
Knowledge of GPU/CPU/DDR/Bus preferred.
Formal verification experience (AND/OR) Low Power Formal Verification experience

📌 Pagls/partl Verification Engineerst Rm 4445 Bengaluru (India)
🏢 Source right
📍 India