25 Sep
|
Modernize Chip Solutions (MCS)
|
Bengaluru
25 Sep
Modernize Chip Solutions (MCS)
Bengaluru
Authoring and owning 3rd party IP integration.
Multi-domain CDC analysis
ASEP 8-port interface: 32-to-16-bit width adaptation, async FIFO design, stype routing, SOP/EOP framing
APB/SOC slave bus bridge; register map ownership; RGGEN-based CSR methodology
System Verilog (RTL and assertions), lint (Cadence HAL/SpyGlass), linting closure, cadence CDC tool
Working knowledge of ASA-ML DLL, PCS, OAM, PTB, and ASEP layers; PHY datasheet/spec fluency
Add MBIST/LBIST and redundancy etc. safety mechanism to make whole chip complied to FuSa requirements
Note: Don't share RTL-verlog coding, FPGA and only flow exp(lint/CDC/RDC) profiles. Must have SOC integration exp with flow exp.
📌 Rtl Soc Integration Bengaluru
🏢 Modernize Chip Solutions (MCS)
📍 Bengaluru