We’re looking for someone with robust hands-on experience in ATPG, scan, and DFT flows, with the ability to independently handle DFT tasks and debug complex issues.Must Have:3+ years of SoC/ASIC Digital Design with DFT experienceStrong hands-on ATPG experienceATPG coverage analysis and fault coverage improvementATPG pattern verification using no-timing and SDF-annotated simulationsDebugging simulation miscompares and root-cause analysisKnowledge of scan chain insertion and DFT insertion flowsGood understanding of MBISTStrong problem-solving and systematic debugging skillsGood to Have:DFT architecture experienceCompression scan, LBIST, and advanced scan technologiesJTAG 1149.1/1149.6, IEEE 1500, IEEE 1687Hands-on experience with Cadence DFT tools/flowsSynthesis and Verilog testbench debuggingTiming analysis and equivalency checks
📌 Dft Engineer (Chennai)
🏢 LanceSoft
📍 Chennai
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