Company Description THINSIL is a semiconductor company focused on delivering cutting-edge solutions and driving innovation across the industry. Since its founding on March 1, 2018, THINSIL has grown through strong technical expertise and cooperative engineering culture.

The company partners with leading global customers such as AMD, ADI, EMM, Qualcomm, Siliconch, and Samsung, providing high-quality design and analysis services. Team members at THINSIL work on advanced technologies that shape the future of semiconductor products, contributing directly to impactful solutions for end users.

Role Description As a Static Timing Analysis Engineer at THINSIL, you will perform detailed timing analysis for complex digital designs, ensuring that all paths meet performance and reliability requirements. In this full-time, on-site role based in Bengaluru South, you will run STA tools, interpret timing reports, and collaborate with design and physical implementation teams to resolve timing violations.

Your day-to-day tasks will include setting up timing constraints, analyzing clock domains, validating timing closure across different process, voltage, and temperature corners, and supporting sign-off activities. You will also contribute to improving analysis methodologies, document findings,



and communicate results clearly to cross-functional stakeholders.

Qualifications

- Candidates should possess strong analytical skills and a structured problem-solving approach.
- Candidates should possess skills in failure analysis to identify root causes of timing issues and evaluate design robustness.
- Candidates should possess data analysis skills to interpret timing reports, logs, and simulation outputs effectively.
- Candidates should possess testing skills for validating timing behavior and supporting verification and sign-off processes.
- Candidates should possess skills in simulations, including running timing simulations and assessing performance across PVT corners.
- Hands-on experience with industry-standard STA tools (e.g., PrimeTime or equivalent) and timing constraint formats (SDC).
- Good understanding of digital design fundamentals, clocking, setup/hold, and signal integrity concepts.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field.
- Ability to work collaboratively in on-site teams, communicate clearly, and manage multiple tasks in a fast-paced environment.

📌 Static Timing Analysis Engineer (Bengaluru)
🏢 THINSIL
📍 Bengaluru