We are looking for an experienced DFT Technical Lead/Manager to drive the strategy, architecture, implementation, and validation of Design-for-Test methodologies for next-generation SoCs and ASICs.

Key Responsibilities

DFT Architecture & Strategy
Define and drive the overall DFT architecture for complex SoCs, multi-core, and multi-die designs.
Develop test strategies covering Scan, ATPG, MBIST, LBIST, and IJTAG (IEEE 1687).
Drive trade-offs across test coverage, area overhead, pin count, test time, and manufacturing cost.
Establish DFT methodologies and flows aligned with product and manufacturing requirements.

DFT Implementation & Verification
Lead DFT insertion and verification at both block and full-chip levels.
Generate and optimize high-quality ATPG patterns, including Stuck-at, Transition Delay, Path Delay, and Cell-Aware testing.




Drive pre-layout and post-layout Gate-Level Simulation (GLS) with timing annotations.
Own DFT timing constraints and work closely with Physical Design and STA teams to achieve timing closure.
Debug and resolve complex DFT implementation and verification issues.

Ideal Profile
Robust experience in DFT/Design-for-Test for complex SoCs or ASICs.
Hands-on expertise in Scan, ATPG, MBIST, LBIST, IJTAG/IEEE 1687, and DFT verification.
Experience with full-chip DFT implementation and test architecture.
Solid understanding of DFT timing, ATPG coverage, pattern generation, GLS, and silicon debug.
Experience working with Physical Design, STA, Verification, and ATE teams.

📌 Dft Technical Lead Bengaluru (India)
🏢 Mirafra Technologies
📍 India