We are seeking an experienced Physical Design Lead to drive end-to-end RTL-to-GDSII execution for complex SoCs across advanced nodes, with solid ownership of PPA, timing closure, and team leadership.
Key Responsibilities:
Own complete RTL-to-GDSII flow: floorplan, place, CTS, route, signoff
Drive PPA optimization, timing, SI, IR/EM closure
Lead and mentor a team of PD engineers; manage schedules and deliverables
Interface with RTL, DFT, STA, Verification, Foundry, and Signoff teams
Handle ECOs, tapeout readiness, and design reviews
Improve PD methodologies, flows, and automation
Skills & Experience:
Robust hands-on PD expertise with Innovus / ICC2 / FusionCompiler / Tempus / PrimeTime / Etc.
Experience in 28nm to 3nm nodes
Solid scripting skills (TCL, Python/Perl/Shell)
Proven ownership of block or full-chip tapeouts
Education:
B.E./B.Tech/M.Tech in Electronics or related fields