Senior Verification Engineer (Vasanthanagar)

Senior Verification Engineer (Vasanthanagar)

27 Sep
|
ACL Digital
|
Vasanthanagar

27 Sep

ACL Digital

Vasanthanagar

IP/ SoC Verification Engineer

: Must have good knowledge on the verification flows. Excellent hands-on debug skills and problem solving attitude.. Experience of working in complex test-bench/model in

Verilog , System Verilog or

SystemC Experience of working on

Functional

Verification, SoC Verification, Emulation. Good in programming :

System Verilog , PLI/ DPI interface, C/C++, PERL/Shell script, assembly language. OVM / UVM

Methodology knowledge and experience. Must have positive communication skills and the ability to work in a team environment. Preferably having experience in architecture such as x86 or ARM domain based SOCs having

SOC / IP performance verification background is added plus.

Experience : 4 to 12 Years Location : Bangalore

📌 Senior Verification Engineer (Vasanthanagar)
🏢 ACL Digital
📍 Vasanthanagar

Reply to this offer

Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.

Subscribe to this job alert:

Get the latest job offers by email for: senior verification engineer (vasanthanagar) / vasanthanagar

Subscribe to this job alert:

Get the latest job offers by email for: senior verification engineer (vasanthanagar) / vasanthanagar