- We are seeking a Senior FPGA Design Engineer specializing in porting, adapting, and optimizing complex IP cores to FPGA targets. In this role, the engineer will be responsible for the migration of ASIC RTL, System level models, or third-party IP into robust FPGA architectures, specifically managing high-speed protocol integration and advanced timing closure. The engineer will also be responsible for evaluating IP compatibility, rewriting or wrapper-engineering RTL to fit target FPGA fabrics, and ensuring the final system meets strict performance and timing requirements.
Technical Skills:
- Languages: Robust proficiency in hardware description languages like Verilog, SystemVerilog or VHDL
- Vendor Toolchains: Experience with major design suites such as Xilinx Vivado, Altera Quartus etc.
- Simulation & Verification: Proficiency with tools like ModelSim, VDS or functional verification methodologies (UVM/Self-checking test benches)
- Timing & Closure: Deep understanding of static timing analysis (STA), Clock domain crossing (CDC) techniques and creating timing constraints.
- Interfaces and Protocols: Familiarity with high-speed serial and parallel protocols like PCIe, USB (10G/10G), DDR4/DDR5 memory, I2C and SPI.
Requirements:
- 8+ years of hands-on digital design and FPGA implementation experience (Senior Level)
- Bachelor's or Master's Degree in Electronics Engineering or similar