Job DescriptionHiring Location: Bangalore

NExperience: 8-12 Years

NWe are seeking a Staff DFT Engineer who can own and drive the complete DFT strategy for complex SoCs from architecture through production silicon. This role requires deep hands-on expertise, robust technical judgment, and the ability to lead and mentor junior engineers while collaborating cross-functionally with design, PD, validation, and manufacturing teams.

NThe ideal candidate operates independently, makes architecture-level decisions, and is accountable for test quality, coverage, and silicon readiness.

NResponsibilities:

NDFT Architecture & Planning

N

n
- Own DFT architecture definition at chip and subsystem level
N
- Define scan, compression, LBIST, MBIST, boundary scan, and test access strategies
N
- Drive testability requirements early in the RTL design phase
N
- Balance coverage, test time, power, area, and schedule tradeoffs
N

nDFT Implementation(End-to-End Ownership)

N

n
- Lead and execute:
N
- Scan insertion, stitching, and DRC closure
N
- ATPG (stuck-at, transition, path delay)
N
- Test compression and pattern optimization
N
- Own DFT signoff including coverage, IR drop, power, and timing impacts
N
- Debug and resolve DFT issues across RTL, synthesis, P&R;, and gate-level stages
N

nATPG & Test Quality

N

n
- Generate, analyze, and optimize ATPG patterns
N
- Achieve high fault coverage with minimal pattern count
N
- Review and sign off on:
N
- Fault coverage reports
N
- Pattern volume and testtime
N
- Diagnose coverage holesand drive design or methodology fixes
N

nSilicon Bring-Up &Production; Support

N

n
- Support first silicon bring-up, failure analysis, and yield ramp
N
- Debug scan, BIST, and tester-related failures
N




- Collaborate with ATE and manufacturing teams to improve yield and test robustness
N
- Drive ECOs for DFT-related silicon issues
N

nTechnical Leadership & Mentorship

N

n
- Act as DFT technical lead for one or more chips
N
- Guide and review work of junior and senior DFT engineers
N
- Define best practices, checklists, and reusable DFT methodologies
N
- Provide technical direction and design reviews
N

nCross-Functional Collaboration

N

n
- Work closely with:
N
- RTL designers
n
- Physical design (PD)
N
- Functional verification
N
- Product engineering andmanufacturing
N
- Communicate DFT requirements and risks clearly to stakeholders
N

nPreferred/Nice-to-Have Experience:

N

n
- Experience with high-volume production test, ATE bring-up, and test cost optimization.
N
- Exposure to safety-critical applications (automotive, industrial) and standards (e.G., ISO 26262) from a test/reliability standpoint.
N
- Experience with on-chipdebug, trace, and design-for-debug features.
N
- Scripting skills in Python/Tcl/Perl for DFT automation, log analysis, and flow integration.
N
- Prior experience mentoring or leading small DFT teams or task forces.
N

nQualifications andExperience:

N

n
- Proven experiencein leading DFT teams through end-to-end SoC execution, from architecture to silicon bring-up.
N
- Demonstrated expertise in developing DFT architecture from scratch for complex SoC designs.
N
- Strong team management and leadership experience with a track record of mentoring and growing engineering talent.
N
- Bachelor's or Master's degree in Electrical/Electronics Engineering or a closely related field.
N
- 7+ years of hands-on experience in DFT methodologies and industry-standard test techniques.
N
- Deep knowledge and hands-on experience with:
N

📌 Hiring: Dft Engineer (Bengaluru)
🏢 Capgemini Engineering
📍 Bengaluru