FPGA Embedded Engineer Xilinx Zynq (PS + PL)

Defense & Aerospace Embedded Systems | Mid-Level | 3–6 Years

Position Overview

Job Title

FPGA Embedded Engineer (Xilinx Zynq)

Experience

1-3 Years (Relevant FPGA/Embedded)

Location

Hyderabad, India (On-site)

Engagement Type

Full-Time

Domain

Defense Electronics | Airborne Radar | Weather Systems | Signal Processing

Primary Platform

Xilinx Zynq SoC (ADRV9361-Z7035 / Zynq-7000 / Zynq UltraScale+)

Toolchain

Xilinx Vivado Design Suite, Vitis IDE, Xilinx SDK

About the Role

We are looking for a sharp, hands-on FPGA Embedded Engineer with proven experience on Xilinx Zynq SoC platforms. The role demands equal strength on both the Processing System (PS) side - ARM Cortex-A based embedded software - and the Programmable Logic (PL) side - RTL design, IP integration, and timing closure in Vivado. Candidates should also have a minimum of 1 year of experience as an SDR (Software Defined Radio) Developer. You will be working on mission-critical embedded systems including weather radar signal acquisition pipelines, airborne sensor interfaces, and real-time data transfer architectures for defense and aerospace customers.

Key Responsibilities

A. Processing System (PS) — ARM Cortex-A Embedded Software

- Develop and maintain embedded software on ARM Cortex-A9/A53 running on Zynq PS
- Write bare-metal or Linux-based C/C++ drivers for peripherals: Ethernet, UART, SPI, I2C, AXI
- Implement real-time Ethernet data acquisition pipelines (UDP/TCP receive, live processing)
- Design and validate PS-to-PL data transfer over AXI4, AXI4-Stream, and AXI-Lite interfaces
- Port and maintain U-Boot / FSBL / PetaLinux BSP; manage BOOT.bin generation and SD/QSPI boot configuration
- Develop interrupt-driven and DMA-based I/O handling for high-throughput data paths
- Integrate and test PS-side communication stacks: Ethernet, RS-232/422, custom protocols
- Write application-layer software for signal data processing and command-response handling

B. Programmable Logic (PL) — RTL Design & Vivado

- Design, simulate, and synthesize digital logic in VHDL / Verilog using Xilinx Vivado
- Develop and integrate AXI-compliant custom IP cores for data acquisition and control interfaces
- Work with Vivado IP Integrator (Block Design) to assemble subsystems: AXI Interconnect, DMA, GPIO, UART, IIC
- Close timing constraints — experience with SDC constraints, Vivado timing analysis, and resolving critical path violations
- Implement high-speed data paths for radar signal feeds (e.g., 120+ Mbps streaming data)
- Design and integrate AXI DMA pipelines for zero-copy PSPL memory transfers
- Configure and validate MIG (Memory Interface Generator) for DDR3/DDR4 SDRAM on PL side where applicable
- Perform FPGA resource utilization optimization (LUT, FF, BRAM, DSP)
- Write and maintain testbenches in VHDL/Verilog; run functional simulation in Vivado Simulator or ModelSim

C. System Integration & Bring-up

- Perform board bring-up, JTAG debug, and hardware validation on custom and COTS Zynq boards
- Integrate PS software and PL bitstream; validate end-to-end data flow from sensor interface to application layer




- Debug PSPL interface issues using ILA (Integrated Logic Analyzer) and VIO cores in Vivado
- Support hardware-in-loop testing and field trials for radar/weather systems
- Collaborate with hardware design team on pin mapping, IO standards, and PCB constraints

Technical Requirements Must-Have — Non-Negotiable

Area

Requirement

Proof We Look For

Zynq PS

ARM Cortex-A embedded C/C++ on Zynq (bare-metal or Linux)

Delivered PS driver or application on Zynq platform

Zynq PL

RTL in VHDL or Verilog, synthesized and implemented in Vivado

Closed timing on at least one Vivado project

AXI Interface

AXI4 / AXI4-Stream / AXI-Lite integration (custom IP or IP integrator)

AXI4 DMA or custom IP with working PSPL transfer

Vivado Suite

Vivado Design Suite for synthesis, implementation, bitstream generation

Daily Vivado use for 2+ years

PS Boot Flow

FSBL / U-Boot / BOOT.bin / PetaLinux or Yocto BSP

Self-managed boot image build and SD/QSPI flash

Data Interfaces

Ethernet (UDP/TCP), UART, SPI, I2C on PS side

Working driver or application using these interfaces

Debug

ILA / VIO for in-system PL debug; JTAG-based PS debug

Used ILA to root-cause a real integration bug

Strong Advantage (Differentiating Skills)

- Experience on Xilinx Zynq ADRV9361-Z7035 or similar SDR/radar SoC platforms
- PSPL interface design for real-time radar or weather signal acquisition
- High-throughput AXI DMA design (streaming data from FPGA fabric to DDR / PS memory)
- MIL-STD-1553B IP integration on Zynq PL (AXI-based IP cores: Sital, Holt, etc.)
- Embedded Linux device driver development (kernel module or character driver for custom PL IP)
- Signal processing blocks in RTL: FIR/IIR filters, FFT pipeline, threshold logic
- Multi-layer PCB constraint awareness (IO standards, voltage banks, SelectIO)
- Qt/QML or similar GUI layer interfacing with PS-side data streams over Ethernet

Positive to Have

- Experience with Zynq UltraScale+ (MPSoC) or Versal platforms
- OpenCL / HLS (High-Level Synthesis) for algorithm acceleration on PL
- Knowledge of DO-178B/C or DO-254 processes in FPGA-based avionics
- Familiarity with ICD-based protocol parsing (binary frame formats, message definitions)
- Experience with Xilinx SDK / Vitis Unified IDE migration

Experience Benchmark by Year Band

Band

What We Expect

3 – 4 Years

Independent ownership of PS-side driver/application development on Zynq. Can build a working Vivado project with AXI IP integrator. Has delivered at least one end-to-end PS+PL integrated feature.

4 – 5 Years

Has closed timing on a non-trivial PL design. Independently managed PetaLinux BSP or custom boot image. Experience with ILA debug in a real hardware bring-up situation.

5 – 6 Years

Designed a custom AXI IP core.



Led a PS+PL integration milestone on a product. Has worked with high-speed data paths (radar, SDR, or similar). Exposure to defense or aerospace domain preferred.

Skills Summary Matrix

Category

Tools & Technologies

Hardware Platform

Xilinx Zynq-7000, Zynq UltraScale+ MPSoC, ADRV9361-Z7035, Custom Zynq Boards

PL Languages

VHDL, Verilog (SystemVerilog awareness is a plus)

PS Languages

Embedded C, C++, Python (scripting/automation)

EDA Tools

Xilinx Vivado Design Suite, Vitis IDE, Xilinx SDK, ModelSim / Vivado Simulator

IP & Interfaces

AXI4, AXI4-Stream, AXI-Lite, AXI DMA, MIG, Ethernet (GEM), UART, SPI, I2C, GPIO

OS / BSP

PetaLinux, Embedded Linux, Yocto (basic), Bare-metal (standalone BSP)

Debug Tools

ILA, VIO, JTAG (Vivado Hardware Manager), GDB, Serial console

Protocols

Ethernet UDP/TCP, RS-232, RS-422, MIL-STD-1553B (exposure), Custom binary ICD protocols

Version Control

Git, GitHub

Domain

Defense Electronics, Airborne Radar, Weather Radar, Signal Acquisition, Sensor Interfaces

What You Will Work On

Our active projects that you will directly contribute to:

Project

Your Contribution Area

Weather Tester System (Radar)

PS-side Ethernet data acquisition, AXI-based PSPL transfer, real-time radar signal pipeline on Zynq ADRV9361-Z7035

Situational Awareness Suite (Airborne)

Sensor data interface on FPGA, embedded software integration, protocol handling for radar / weather / AIS feeds

MIL-STD-1553B Integration

AXI-based 1553B IP integration on Zynq PL, PS-side C driver development, AXI register interface validation

Custom OBC Development

High-performance FPGA + CPU + GPU compute node — FPGA fabric design, AXI interconnect architecture, PS software stack

Edge AI Payload Systems

FPGA pre-processing pipeline for hyperspectral camera feed, DMA to GPU memory, real-time data handoff

Who Is Not a Fit

- Candidates with only Altera/Intel FPGA experience and no Xilinx Vivado hands-on
- Profiles that are exclusively PS-side (software engineers with no RTL exposure)
- Profiles that are exclusively PL-side (RTL designers with no ARM embedded software experience)
- Anyone below 3 years of hands-on Zynq/FPGA experience
- Those above 6 years are expected at a senior/lead level and will be evaluated under a separate band

Interview & Evaluation Process

Round

Focus

Round 1 — Technical Screen (30 min)

Quick PS+PL fundamentals: AXI, Zynq architecture, boot flow, VHDL/Verilog basics

Round 2 — Deep Technical (60–90 min)

Live design problem: AXI IP integration or PS driver architecture; timing analysis discussion; debug scenario

Round 3 — Project Review (45 min)

Walk-through of candidate's most relevant Zynq project: design choices, challenges, timing closure, bring-up issues

Round 4 — Fit & Domain (30 min)

Domain alignment: defense/aerospace context, field trial exposure, documentation discipline

Confidential — Internal Use Only

This JD reflects the technical requirements derived from active project needs. Both PS (ARM Cortex-A) and PL (Vivado RTL) experience are mandatory — this is not a pure software nor a pure RTL role.

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