Design Verification: PAGLS (Bengaluru)

Design Verification: PAGLS (Bengaluru)

27 Sep
|
Mirafra Software Technologies
|
Bengaluru

27 Sep

Mirafra Software Technologies

Bengaluru

Design Verification: PAGLS

Location: Bangalore

- Subsystem/SoC level digital verification using constrained-random coverage methodologies at both RTL and Gate Level with UPF

- SOC,GLS and PAGLS

- Experience with Power aware(UPF) verification at RTL And GLS simulations

- Experience in writing Test Plans independently

- Experience in writing/updating Verification Testbench

- Experience with debugging RTL & Gate level simulations

- Experience with Functional Coverage &Code; Coverage

- Experience with Scripting in perl, python, tcl

- Experience in planning Verification architecture, review testbench/ testplans with juniors, identify coverage gaps, propose alternate methods for coverage

- Should have been involved in leading a chip DV effort

- Should have been self-driven and quick learner

Experience (years) : 4-12 years

Education Qualification

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

📌 Design Verification: PAGLS (Bengaluru)
🏢 Mirafra Software Technologies
📍 Bengaluru

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