- Exposure to DFT architecture and design for complex SoCs.
- Positive working knowledge of ATPG tools, including Mentor Tessent / TK or equivalent platforms.
- Exposure to static timing analysis and timing closure.
- Excellent hands-on debug ability and strong scripting skills.
- Experience building DFT reporting frameworks, coverage dashboards, or automated quality gates.
Secondary skills:
- Recommended experience profile: B.E./B.Tech./M.E./M. Tech. in Electrical or Electronics Engineering with relevant DFT / ATPG experience.
- Role Summary
- As a key member of the Server SoC DFT team, the successful candidate will play a significant role in ensuring the quality of next-generation SoCs through structural DFT, ATPG, LBIST, and execution-focused automation. In addition to owning core ATPG deliverables, this engineer will be expected to improve the speed, quality, and repeatability of manufacturing test pattern generation, coverage review,
and debug closure by using strong scripting, reporting frameworks, and selective AI-assisted analysis.
Primary Responsibilities
- Work closely with the Architecture team to understand DFT architecture and implementation requirements.
- Interface with Design teams to ensure DFT design rules and implementation guidelines are met.
- Partner with Physical Design teams to ensure correct DFT implementation and timing closure.
- Generate high-quality manufacturing test patterns for stuck-at and transition fault models using on-chip test compression techniques.
- Simulate and verify ATPG and LBIST patterns and support sign-off readiness.
- Analyze coverage loss mechanisms and work with cross-functional stakeholders to drive design changes that improve ATPG coverage.
- Support Product Engineering on pattern delivery, silicon bring-up, and post-silicon debug.
- Develop, enhance, and maintain scripts, reporting utilities, and execution checkers required for efficient DFT delivery.