Hi,
We are hiring Synthesis Engineers with 2 to 6 years of experience for our VLSI team.
Role: Synthesis Engineer
Experience: 26 Years
Location: Bangalore & Hyderabad
Notice Period: Immediate to 30 Days preferred
Key Skills:
- Hands-on experience in RTL Synthesis
- Strong knowledge of Synopsys Design Compiler (DC) / Fusion Compiler (FC)
- Positive understanding of SDC constraints and timing concepts
- Experience in timing, area and power optimization
- Good knowledge of Verilog/SystemVerilog
- Experience with Tcl/Perl/Python scripting
- Understanding of RTL-to-GDSII flow
- Good debugging and problem-solving skills
Interested candidates, please share your updated resume along with the below details:
Total Experience:
Relevant Synthesis Experience:
Current Location:
Preferred Location:
Current CTC:
Expected CTC:
Notice Period:
Contact Number:
Please share your updated resume at
[email protected].
📌 Synthesis Engineer (Hyderabad)
🏢 Mirafra
📍 Hyderabad