Senior LEC/CLP Engineer
Experience:- 3 to 6 Years Notice Period:- 0 to 45 Days Location:- Bangalore
Role Overview:
We are seeking a experienced
LEC / CLP Engineer
with expertise in
Logic Equivalence Check (LEC)
and
Conformal Low Power (CLP)
methodologies.
Key Responsibilities: Lead
Logic Equivalence Check (LEC)
and
Low Power verification (CLP)
activities across block and full-chip levels.
Define and implement
LEC/CLP methodologies
using industry-standard tools (Cadence Conformal, Synopsys Formality, etc.).
Validate low-power architecture,
UPF/CPF constraints , and intent across multiple domains.
Collaborate with RTL, Synthesis, and Physical Design teams to resolve mismatches.
Review and debug
LEC/CLP failures
to drive sign-off closure.
Automate verification flows using
Python/Perl/TCL scripting .




Required Skills
Expertise with tools like
Cadence Conformal, Synopsys Formality, or equivalent . Strong understanding of
RTL-to-netlist equivalence ,
low-power UPF/CPF verification , and
multi-power domain SoCs . Proven track record in debugging
LEC/CLP failures
and collaborating across design teams. Proficiency in
scripting (Python, Perl, TCL)
for automation. Solid analytical, problem-solving
Preferred Qualifications: Master’s or Bachelor’s in
Electronics / Electrical / VLSI Engineering . Experience in advanced nodes (7nm and below). Exposure to
low-power design methodologies
and
complex SoC projects .

📌 Senior LEC / CLP Engineer (India)
🏢 Leadsoc Technologies
📍 India