Hiring: Dft Engineer (Hyderabad)

Hiring: Dft Engineer (Hyderabad)

28 Sep
|
smartsoc solutions
|
Hyderabad

28 Sep

smartsoc solutions

Hyderabad

In this role, you will own and drive Design for Test (DFT) strategy, architecture, and implementation across the full chip lifecycle.

Responsibilities

- Execute and support Design-for-Test (DFT) activities, including Scan Insertion, ATPG, and OCC Integration.
- Perform DRC debugging, test coverage analysis, and simulation debugging across different stages of the DFT flow.
- Analyze and resolve issues related to testability, fault coverage, and pattern generation.
- Work with advanced DFT methodologies such as SSN, IJTAG, ICL, and PDL.
- Collaborate with cross-functional teams to ensure seamless DFT integration and effective issue resolution.
- Drive continuous improvements in DFT flows, methodologies, and debugging efficiency.

- Experience: 3 to 8 yrs

Required Skills:Key Responsibilities:

- Define and implement DFT architecture for large, complex SoCs/ASICs
- Own end-to-end DFT strategy and execution including Scan, ATPG, MBIST, LBIST, JTAG, and Boundary Scan
- Perform Scan insertion, ATPG pattern generation, compression, and fault grading




- Develop and maintain DFT specifications and ensure compliance throughout the design cycle
- Integrate and verify DFT logic at RTL and gate-level (GLS)
- Collaborate with verification teams for pattern simulation, validation, and debug
- Work closely with physical design teams to meet timing, power, and area constraints
- Debug silicon bring-up issues and support ATE test pattern validation
- Drive improvements in DFT methodologies and flows
- Mentor junior engineers and provide technical leadership
- Strong expertise in Scan, ATPG, BIST (MBIST/LBIST), JTAG/Boundary Scan, and compression techniques
- Hands-on experience with DFT tools such as Synopsys DFT Compiler, Tetramax, Tessent, or equivalent
- Solid understanding of RTL design, synthesis, and verification flows
- Familiarity with STA and physical design constraints related to DFT
- Experience in silicon bring-up and ATE test pattern generation
- Strong debugging and analytical skills

📌 Hiring: Dft Engineer (Hyderabad)
🏢 smartsoc solutions
📍 Hyderabad

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