Senior Designer

Bangalore, KarnatakaChennai, Tamil Nadu

Job Summary

JD is Role: Signal Integrity & Power Integrity

SI Minimum Requirements:
3-8 years experience.
Strong knowledge in Signal Integrity and Power Integrity fundamental concepts.
Strong experience in Package and PCB modelling is required.
Performs Transmission line & Via modelling and carry out experiments to validate modelling outcomes and methodologies.
Deep Understanding of S-parameter & its modelling concepts for Single ended and differential interfaces.
Experience in simulating (FD/TD) memory interfaces for Board and Package is required (DDR4/LPDDR4)
Experience in simulating (FD/TD) High Speed Serial IO interfaces for Board and Package is required (PCIe Gen3/4, SATA Gen3, USB3/3.1 and Display Interfaces etc.)
Good knowledge of Power Delivery Network, impedance profile analysis, IR Drop Analysis, and time domain Analysis.
Experience in extracting the PDN model of package and PCB power rails and perform decoupling capacitor optimization, Loop inductance analysis.
Should be able to analyze and review the layout files related to Signal integrity and Power Integrity problems.
Should be able to provide practical solutions to PCB/Package design team based on simulation results and analysis.
Robust knowledge in simulation tools specifically Hspice, Sigrity (2.5D and 3D-EM Must), ADS and other tools like Ansys SIwave, HFSS 3D.
PI Minimum Requirements:
PDN mechanism
S-parameter and their properties
PI metrics, namely Rpath (DC R), IR drop, current density, droop, overshoot, load line (impedance profile)
VR PI modeling
DC, AC and Transient analysis using the tools in #1
PDN design optimization and guideline

Solid tool skillsets (requiring minimum to no supervision) in
Cadence PowerDC, PowerSI, Allegro
Ansys SiWave, HFSS
Synopsys HSpice
Keysight ADS
SimPlis/SIMetrix





Key Responsibilities

JD is Role: Signal Integrity & Power Integrity

SI Minimum Requirements:
3-8 years experience.
Strong knowledge in Signal Integrity and Power Integrity fundamental concepts.
Strong experience in Package and PCB modelling is required.
Performs Transmission line & Via modelling and carry out experiments to validate modelling outcomes and methodologies.
Deep Understanding of S-parameter & its modelling concepts for Single ended and differential interfaces.
Experience in simulating (FD/TD) memory interfaces for Board and Package is required (DDR4/LPDDR4)
Experience in simulating (FD/TD) High Speed Serial IO interfaces for Board and Package is required (PCIe Gen3/4, SATA Gen3, USB3/3.1 and Display Interfaces etc.)
Good knowledge of Power Delivery Network, impedance profile analysis, IR Drop Analysis, and time domain Analysis.
Experience in extracting the PDN model of package and PCB power rails and perform decoupling capacitor optimization, Loop inductance analysis.
Should be able to analyze and review the layout files related to Signal integrity and Power Integrity problems.
Should be able to provide practical solutions to PCB/Package design team based on simulation results and analysis.
Solid knowledge in simulation tools specifically Hspice, Sigrity (2.5D and 3D-EM Must), ADS and other tools like Ansys SIwave, HFSS 3D.
PI Minimum Requirements:
PDN mechanism
S-parameter and their properties
PI metrics, namely Rpath (DC R), IR drop, current density, droop, overshoot, load line (impedance profile)
VR PI modeling
DC, AC and Transient analysis using the tools in #1
PDN design optimization and guideline

Solid tool skillsets (requiring minimum to no supervision) in
Cadence PowerDC, PowerSI, Allegro
Ansys SiWave, HFSS
Synopsys HSpice
Keysight ADS
SimPlis/SIMetrix

Skill Requirements

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