Job DescriptionDesign Verification Engineer - Senior / Lead / Sr. Lead NJob Description: Nn Must have good knowledge on the verification flows. N Excellent hands-on debug skills and problem solving attitude.. N Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC N Experience of working on Functional Verification, SoC Verification, Emulation N Good in programming: System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language. N OVM/UVM Methodology knowledge and experience N Must have valuable communication skills and the ability to work in a team environment. N Preferably having experience in architecture such as x86 or ARM domain based SOCs Nnhaving SOC/IP performance verification background is added plus NExperience: 4 to 12 Years NLocation: Bangalore / Hyderabad NWork Mode: Work from Office (WFO)
📌 Design Verification Engineer (Vasanthanagar)
🏢 ACL Digital
📍 Vasanthanagar
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