- Verification of SOC RTL : FW-HW co-verification at SOC level, valuable understanding of SOC boot flow, integration level verification,
- Development and verification of post-si validation sequences using C/C++,
- Create methodology-based (UVM) verification testbenches and components from scratch at SOC level along with re-usability of IP level components.
- Experienced with Verilog, System Verilog, and C or C++
- Good understanding of JTAG protocol
Mandatory Skills:
- Minimum 5 years relevant experience in pre silicon RTL Verification needed along with Verilog, JTAG and UVM exp.
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