- Strong in RTL digital design with Verilog/VHDL.
- Strong familiarity with FPGA Vivado Design creation, taking it through Synthesis, implementation, bit-stream generation.
- Thorough understanding of the design constraints ( timing , IO LOC, placement etc.,)
- Knowledge of system-level architecture including buses like AXI/AHB/CHI/ACE5, bridges, video IPs like ISP/Encoder/Decoder and peripherals such as USB and Ethernet
- Excellent waveform debug skills using front end industry standard design tools like ILA, verification waveforms.
- Demonstrate the ability to work with cross-functional teams
- Proficiency in Unix setting
- Good knowledge in scripting(Perl/Tcl/Python)
and automation of verification flows/process
- Familiarity with presi platforms would be useful.
Mandatory Skills:
- RTL designer is expected to have strong expertise on Xilinx Vivado tools.
- IP understanding, System level design understanding, IP product guide understanding.
- Version management tools(Perforce,Github) , AMBA protocols(AXI4,AXIS) and strong Linux skills
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