DFT with Cadence Tool:

Key Responsibilities

DFT Architecture & Planning

- Define and develop DFT strategy for complex ASIC and SoC designs.
- Create DFT specifications and test architecture documents.
- Drive DFT implementation activities from RTL through tapeout.
- Collaborate with RTL, Design Verification, Physical Design, STA, and Silicon Validation teams.
- Ensure high fault coverage while meeting PPA requirements.
- Participate in architecture reviews and DFT signoff activities.

Scan Insertion & Test Compression

- Design and implement scan architecture.
- Perform scan chain insertion and optimization.
- Implement scan compression methodologies.
- Analyze and debug scan chain violations.
- Support scan-chain reordering and physical-aware DFT implementation.
- Optimize test time and tester memory utilization.

Key Areas

- Scan Insertion
- Scan Stitching
- Scan Partitioning
- Test Compression
- EDT Architecture
- Scan Reordering
- Scan Verification

ATPG & Fault Coverage

- Generate ATPG patterns for production testing.
- Achieve targeted fault coverage goals.
- Perform fault simulation and coverage analysis.
- Debug ATPG violations and improve testability.
- Optimize pattern count and tester efficiency.

ATPG Activities

- Stuck-at ATPG
- Transition ATPG
- Path Delay ATPG
- Cell-Aware ATPG
- Bridging Fault Analysis
- Fault Grading
- Fault Simulation
- Pattern Debugging

MBIST Implementation

- Develop and integrate MBIST architecture for embedded memories.
- Support memory repair and redundancy management.
- Implement memory diagnosis and repair solutions.
- Verify MBIST functionality and coverage.

Expertise Required

- MBIST Architecture
- BISR
- BIRA




- Memory Repair Flows
- Memory Diagnosis
- March Algorithms
- Embedded Memory Testing

JTAG & Boundary Scan

- Implement and verify JTAG architecture.
- Integrate TAP controllers and boundary scan logic.
- Support chip-level connectivity testing.
- Debug JTAG and boundary scan issues.

Standards Knowledge

- IEEE 1149.1
- IEEE 1500
- Boundary Scan Architecture
- TAP Controller Implementation

DFT Verification

- Develop DFT verification plans.
- Verify Scan, MBIST, and JTAG functionality.
- Support RTL and Gate-Level verification.
- Create and debug DFT testbenches.
- Validate ATPG patterns using simulation.

Verification Tasks

- RTL Verification
- DFT Verification
- ATPG Validation
- GLS Verification
- Pattern Verification
- Regression Execution

Physical Design & Timing Interaction

- Collaborate with PD teams for DFT-aware implementation.
- Resolve scan-related timing issues.
- Support scan-chain reordering and timing optimization.
- Ensure timing closure of DFT logic.
- Support low-power DFT integration.

Silicon Bring-up & Yield Enhancement

- Support silicon debug activities.
- Analyze tester failures and manufacturing issues.
- Work with Product Engineering and ATE teams.
- Improve yield and test coverage through diagnostics.
- Support volume production readiness.





Mandatory Technical Skills

Cadence DFT Tool Expertise

Strong experience with:

DFT Implementation

- Cadence Modus DFT Software Solution
- Cadence Modus Test Compression
- Cadence Modus ATPG
- Cadence Modus Diagnosis
- Cadence Modus BIST

Verification & Simulation

- Cadence Xcelium
- SimVision Debug Setting

Signoff & Integration

- Cadence JasperGold (Preferred)
- Cadence Conformal LEC
- Cadence Innovus Awareness (Preferred)

Core DFT Competencies

Candidates should have strong experience in:

DFT Architecture

Scan Design

Scan Compression

ATPG

Fault Coverage Analysis

MBIST

JTAG

Boundary Scan

DFT Verification

GLS

Silicon Debug

Yield Analysis

Pattern Validation

Test Coverage Improvement

Production Test Readiness

Roles and Responsibilities
A seasoned technical leader with deep expertise in semiconductor design and development, the Senior Principal Engineer plays a pivotal role in driving innovation across all phases of chip development — from architecture and RTL design to physical implementation, verification, and silicon validation. This role is responsible for setting technical direction on cutting-edge projects, influencing product roadmaps, and ensuring the successful delivery of high-performance, low-power, and cost-effective integrated circuits. Acting as a mentor and technical advisor, the Senior Principal Engineer collaborates with cross-functional teams across architecture, design, verification, DFT, and packaging to push the boundaries of silicon technology while aligning engineering execution with business and product strategies.

📌 DFT Lead (Hyderabad)
🏢 Cyient
📍 Hyderabad