We are seeking a experienced LEC / CLP Engineer with expertise in Logic Equivalence Check (LEC) and Conformal Low Power (CLP) methodologies.
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Key Responsibilities:
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- Lead Logic Equivalence Check (LEC) and Low Power verification (CLP) activities across block and full-chip levels.
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- Define and implement LEC/CLP methodologies using industry-standard tools (Cadence Conformal, Synopsys Formality, etc.).
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- Validate low-power architecture, UPF/CPF constraints, and intent across multiple domains.
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- Collaborate with RTL, Synthesis, and Physical Design teams to resolve mismatches.
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- Review and debug LEC/CLP failures to drive sign-off closure.
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- Automate verification flows using Python/Perl/TCL scripting.
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Required Skills
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Expertise with tools like Cadence Conformal, Synopsys Formality, or equivalent.
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- Strong understanding of RTL-to-netlist equivalence, low-power UPF/CPF verification, and multi-power domain SoCs.
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- Proven track record in debugging LEC/CLP failures and collaborating across design teams.
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- Proficiency in scripting (Python, Perl, TCL) for automation.
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- Solid analytical, problem-solving
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Preferred Qualifications:
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- Master's or Bachelor's in Electronics / Electrical / VLSI Engineering.
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- Experience in advanced nodes (7nm and below).
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- Exposure to low-power design methodologies and complex SoC projects.
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