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- 5+ years of hands-on experience in ASIC/SoC DFT implementation and verification.
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- Strong expertise in Synopsys DFT tools, with mandatory hands-on experience in SMS and SEQ insertion.
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- Strong experience in Scan insertion, Scan compression, DFT DRC debugging, and coverage closure.
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- Hands-on experience with ATPG, including stuck-at and transition fault pattern generation and debugging.
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- Valuable knowledge of MBIST, JTAG/Boundary Scan, test clocks, resets, and multi-clock DFT architectures.
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- Proficiency in TCL/Perl/Python/Shell scripting and experience supporting DFT flows through tape-out.
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