30 Sep
|
smartsoc solutions
|
Hyderabad
30 Sep
smartsoc solutions
Hyderabad
Job Description
In this role, you will own and drive Design for Test (DFT) strategy, architecture, and implementation across the full chip lifecycle.
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Responsibilities
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- Execute and support Design-for-Test (DFT) activities, including Scan Insertion, ATPG, and OCC Integration.
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- Perform DRC debugging, test coverage analysis, and simulation debugging across different stages of the DFT flow.
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- Analyze and resolve issues related to testability, fault coverage, and pattern generation.
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- Work with advanced DFT methodologies such as SSN, IJTAG, ICL, and PDL.
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- Collaborate with cross-functional teams to ensure seamless DFT integration and efficient issue resolution.
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- Drive continuous improvements in DFT flows, methodologies, and debugging efficiency.
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- Experience: 3 to 8 yrs
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Required Skills: Key Responsibilities:
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- Define and implement DFT architecture for large, complex SoCs/ASICs
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- Own end-to-end DFT strategy and execution including Scan, ATPG, MBIST, LBIST, JTAG, and Boundary Scan
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- Perform Scan insertion, ATPG pattern generation, compression, and fault grading
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- Develop and maintain DFT specifications and ensure compliance throughout the design cycle
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- Integrate and verify DFT logic at RTL and gate-level (GLS)
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- Collaborate with verification teams for pattern simulation, validation, and debug
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- Work closely with physical design teams to meet timing, power, and area constraints
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- Debug silicon bring-up issues and support ATE test pattern validation
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- Drive improvements in DFT methodologies and flows
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- Mentor junior engineers and provide technical leadership
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- Strong expertise in Scan, ATPG, BIST (MBIST/LBIST), JTAG/Boundary Scan, and compression techniques
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- Hands-on experience with DFT tools such as Synopsys DFT Compiler, Tetramax, Tessent, or equivalent
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- Solid understanding of RTL design, synthesis, and verification flows
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- Familiarity with STA and physical design constraints related to DFT
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- Experience in silicon bring-up and ATE test pattern generation
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- Solid debugging and analytical skills
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📌 DFT Engineer (Hyderabad)
🏢 smartsoc solutions
📍 Hyderabad