Static Timing Analysis (STA) Lead Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology nodes. As a STA lead you will be working on PrimeTime based flow development and timing closure of multi-million gate SoC design for all modes and all corners in 16/12/7/5nm processes.

Location : Bangalore, KA.

India

Qualification and Skillset Requirements Minimum BE/BS degree (Masters preferred) in Electrical/Electronics Engineering/VLSI

10+ years of practical experience in Static Timing Analysis (STA) using Primetime

Robust fundamentals in digital ASIC design

Understanding of SoC design and implementation methodology and challenges

Understanding of one or more of design flows like Synthesis, Constraint development and STA (Functional and DFT modes) and Physical Design





Good hands on expertise with industry standard implementation tools like – Synopsys PrimeTime, Design Compiler/Fusion Compiler etc. for block as well as top level

Able to work with TCL and Perl scripting and flow automation

Excellent communication and team work Roles And Responsibilities Work on STA methodology and flow development

Develop and integrate constraints at block and SoC level

Provide early feedback on design/timing issues and solutions

Work with Backend team for timing closure during PnR

Work with IP and SoC Design team in optimizing the design to meet timing

Work on timing closure for block/top, all modes/corners by providing timing ECOs etc.

📌 Static Timing Analysis (STA) Lead (Mumbai)
🏢 ScaleFlux
📍 Mumbai